An important aspect of computer aided electronic design is that it provides the designer a means for predicting various performance parameters of the circuit being designed prior to the circuits actually being built. An example of a parameter whose value should be estimated prior to completing the design of a digital circuit is the delay associated with the components (or "blocks") of the circuit. Typically, digital circuit designs are "hierarchical" in that they consist of functional components ("leaf blocks") which compose intermediate level blocks, which in turn compose higher level blocks, and so on. For example, it is well known that a four-bit adder comprises four full adder blocks; which comprise two half adder blocks each; which comprise NAND and INVERTER leaf blocks.
In order to analyze such a design, the design must first be logically represented, or modeled, in the computer. This logical representation is provided by a "data structure". Typically, a delay estimator algorithm traverses the design hierarchy, builds a flattened data structure, and then performs delay computations. A disadvantage with building a flattened data structure is that the data structure becomes extremely large for practical circuits. In addition, building a flattened data structure increases the complexity of the algorithm.
It is therefore an object of the present invention to provide a comparatively simple data structure for logically representing a hierarchical circuit design. It is a further object of the present invention to provide a method of using such a simplified data structure in analyzing the circuit design. The present invention achieves these objectives.